1. Field of the invention
The present invention relates, in general, to a process for fabricating a capacitor in a semiconductor device and, more particularly, to increase of the capacitance per unit area of a cylindrical capacitor through employment of doped amorphous silicon layer and undoped amorphous silicon layer as materials for the capacitor and utilization of an etch selectivity difference therebetween.
2. Description of the Prior Art
Recent trend of high integration of semiconductor devices, especially DRAM devices, has been based on the diminution of cells, which leads to difficulty in providing a capacitor with sufficient capacitance.
A DRAM device, consisting of one MOS transistor and one capacitor, comprises a semiconductor substrate on which a plurality of spaced gates, that is, word lines, and a plurality of spaced metal wires, that is, bit lines are aligned perpendicular to each other in broadwise and lengthwise directions and one capacitor having a contact hole in its center is formed per two gates, extending thereacross.
In such capacitor, a conductor is made mainly of polysilicon and a dielectric material is selected from a group consisting broadly of an oxide, a nitride and an oxide-nitride-oxide (ONO) laminator. In general, a capacitor occupies much area in semiconductor chip. Accordingly, it is one of the most important factors for high integration of DRAM device to reduce the size of the capacitor yet to augment the capacitance thereof.
The capacitance of capacitor is represented by the following equation I: EQU C=( .sub.o .times. .sub.I .times.A)/T I
wherein C means the capacitance of capacitor,
.sub.o is permitivity of vacuum, PA1 .sub.I is dielectric constant of dielectric layer, PA1 A means the surface area of capacitor, and PA1 T means the thickness of dielectric layer.
As taught in Equation I, the capacitance of capacitor is determined by the permitivity of vacuum, the dielectric constant, the area of capacitor and the thickness of dielectric layer. That is, the capacitance can be increased by employing dielectric materials with high dielectric constants, making the dielectric layer thin, and/or increasing the surface area of capacitor.
However, these methods have their own problems in applying for practical semiconductor device. For example, a dielectric material with a high dielectric constant, such as Ta.sub.2 O.sub.5, TiO.sub.2 or SrTiO.sub.3, has been extensively studied but is scarcely applied to a semiconductor device in practice because of uncertainty in its reliability and thin film characteristics, such as dielectric breakdown voltage. In the meanwhile, an extreme reduction in the thickness of the dielectric layer may be a potent factor causing a breakdown in the dielectric layer when operating the device, deleteriously affecting the reliability of the capacitor.
With regard to increase of the surface area, the capacitor is fabricated in the form of pin structure, cylindrical structure or cylindrical structure with a cross section of rectangular frame, wherein a multiplicity of polysilicon layers are so deposited as to connect them with one another. Separately, so-called hemispherical grain polysilicon (hereinafter referred to as "HSG") process was developed in order to increase the surface area of the capacitor. However, those prior techniques for increasing of the surface area cannot secure the capacitance sufficient enough to satisfy the recent trend of high integration of DRAM devices.
In order to better understand the background of the present invention, reference is made to FIG. 1 which shows the process steps for fabricating a conventional cylindrical capacitor. These steps will be generally described in connection with FIGS. 1A through 1C.
With initial reference to FIG. 1A, there are illustrated process steps just before providing the capacitor with a cylindrical shape. For this, first, on a semiconductor substrate 11, a field oxide film 12 for the device isolation, a gate oxide layer 13, a gate electrode 14 and a source/drain region 15 are formed. Then, an interlayer insulation film 16 is formed entirely over the resulting structure. Next, the interlayer insulation film 16 is removed at an area to be predetermined as bit line contact, followed by formation of a bit line 17. On the entire surface of the resulting structure are in sequence formed a planarization layer 18 made of borophosphosilicate glass (hereinafter referred to as "BPSG") and an oxide layer 19. Thereafter, the oxide layer 19, the planarization layer 18 and the interlayer insulation film 16 are in sequence removed at an area to be predetermined as storage electrode contact, so as to form a storage electrode contact hole 20. A first polysilicon layer is deposited so thickly as to fill the contact hole 20, followed by formation of a thick oxide pattern 22 on the polysilicon of the contact hole 20. Using the thick oxide pattern 22 as a mask, the first polysilicon layer is etched, to form a first polysilicon pattern 21.
Next, as shown in FIG. 1B, the resulting structure of FIG. 1A is entirely covered with a second polysilicon layer 23.
Finally, as shown in FIG. 1C, the polysilicon layer 23 is subjected to anisotropic etch to form a polyspacer 24 at the side wall of the oxide pattern 22, followed by removal of the oxide pattern 22 and the oxide layer 19. As a result, there is formed a cylindrical storage electrode 25 consisting of the polysilicon pattern 21 and the polyspacer 24.
As previously mentioned, such conventional cylindrical storage electrode cannot secure capacitance sufficient enough to meet the requirement of highly integrated devices such as those of 64M or 254M DRAM scale.